In fabrication of semiconductor memories, one technique utilized to increase production yield is to provide redundant circuits on the chip to allow for placement of key circuits which prove defective. During testing of the chip, the defective portion of the circuit is identified and the redundant circuit, if one exists, is activated by opening an associated fuse or similar mechanism. The disadvantage to this technique is that only certain circuits on the chip can be given redundancy, which is sometimes impractical from a cost versus yield standpoint.
Redundancy is especially suited for repetitive circuits having a large number of repeating elements arranged in some form of an array, such that one redundant circuit can replace a single defect in any of a large number of circuit elements. One such device is a semiconductor memory array comprised primarily of memory elements arranged in rows and columns with each row of memory elements activated by a single control line or, more commonly, a bit line. The redundant element in the memory array would either be a row of memory elements or a column of memory elements. If, for example, one element in a given row was determined to be defective, this would classify the device as defective. This defective column could then be replaced by a redundant column and the device would be fully operational. This is normally accomplished by deactivating the defective row and addressing the redundant row with the address of the defective row.
To address the redundant row with the address of the defective row requires interconnecting the output of the row decoder associated with the defective column with the bit line of the redundant row or providing a separate programmable decoder for the redundant row. To provide separate interconnects between each of the outputs of the row decoder with the bit line of the redundant row would require a large number of fuse selected interconnects. For example, in a 256 row memory, the row decoder provides 256 decoder outputs for connection to the individual bit lines of the various rows. Therefore, a redundant row would require 256 fuse selectable interconnects, which would require a large number of metal runs on the surface of the silicon chip. The alternate method is to utilize a programmable decoder which is dedicated to the redundant row. A decoder of this type would also require a large amount of circuitry and associated silicon surface area in the memory array.
In view of the above disadvantages with selecting the address for a redundant row in a memory array, there exists a need for a fuse selectable decoder which minimizes the amount of additional circuitry and silicon surface area required to select the redundant row.